Digital signal processing circuit having an adder circuit with carry-outs
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United States of America Patent
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Jan 11, 2011
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N/A
app pub date -
May 12, 2006
filing date -
Dec 29, 2003
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Abstract
An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to the plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; and a second adder coupled to the bitwise adder for adding together the sum set of bits and carry set of bits to produce a summation set of bits and a plurality of carry-out bits, where the second adder is coupled to a second opcode register.
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