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Abstract

The memory control system includes a memory unit, bus master(s), arbiter, and memory controller. The bus masters output bus use request signals, block mode signals, block information, and drive information for data and outputs data corresponding to block/receive read-out data. The arbiter receives request signals and drive information and outputs a master selection signal used to select a bus master to which access is permitted and the drive signal input from the selected bus master. The bus master selection unit receives block mode signals, block information and data corresponding to the bus masters and outputs the block mode signal, block information and bus master data selected according to the master selection signal. The memory controller receives drive information from the arbiter, block mode signal, and block information from the selection unit, and allows data corresponding to respective line block groups to be sequentially-stored in/read out from respective banks.

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First Claim