Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween

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United States of America Patent

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11425201

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Abstract

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A semiconductor device may include a semiconductor substrate and a plurality of shallow trench isolation (STI) regions in the substrate. More particularly, at least some of the STI regions may include divots therein. The semiconductor device may further include a respective superlattice between adjacent STI regions, and respective non-monocrystalline stringers in the divots.

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Patent Owner(s)

Patent OwnerAddress
MEARS TECHNOLOGIES INC189 WELLS AVE 3RD FLOOR NEWTON MA 02459

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Rao, Kalipatnam Vivek Grafton, MA 23 1607

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