Integrated circuit arrangement with layer stack
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United States of America Patent
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Jun 14, 2011
Grant Date -
Nov 30, 2006
app pub date -
May 19, 2006
filing date -
May 19, 2005
priority date (Note) -
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Abstract
An integrated circuit arrangement includes an electrically conductive conduction structure made from copper or a copper alloy. At a side wall of the conduction structure, there is a layer stack which includes at least three layers. Despite very thin layers in the layer stack, it is possible to achieve a high barrier action against copper diffusion combined with a high electrical conductivity, as is required for electrolytic deposition of copper using external current.
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