Dynamic fetch rate control of an instruction prefetch unit coupled to a pipelined memory system
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United States of America Patent
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Issued Date -
Nov 30, 2006
app pub date -
May 27, 2005
filing date -
May 27, 2005
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Dynamic fetch rate control for a prefetch unit 4 fetching program instructions from a pipelined memory system 2 is provided. The prefetch unit receives a fetch rate control signal from a fetch rate controller 8. The fetch rate controller 8 is responsive to program instructions currently held within an instruction queue 6 to determine the fetch rate control signal to be generated.
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