High efficiency trap for deposition process
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United States of America Patent
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Issued Date -
Dec 7, 2006
app pub date -
Jun 6, 2005
filing date -
Jun 6, 2005
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Abandoned
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Abstract
The present invention provides a system, apparatus and method for improving the efficiency of a semiconductor processing system, such as a deposition system by decreasing or substantially eliminating the accumulation of by-products in the apparatus components of the semiconductor processing system. The present invention further relates to improving the efficiency of a foreline trap associated with a semiconductor processing system, wherein the trap removes substantially all of the by-products from the exhaust gas from the processing chamber. In addition, the present invention provides a system, apparatus and method for efficiently clearing traps of accumulated by-products from exhaust gas of a semiconductor processing system.
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