Hybrid arithmetic logic unit
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United States of America Patent
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Nov 2, 2010
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N/A
app pub date -
Aug 18, 2006
filing date -
Dec 5, 2002
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Abstract
Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of a pipelined ALU. Arithmetic operations are performed in two stages: a first stage that produces separate sum and carry results in a first cycle, and a second stage that produces a final result in one or more immediately subsequent cycles. While this produces final results in two or more clock cycles, useable partial results are produced each cycle, thus maintaining a one operation per clock cycle throughput.
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