Importance

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Abstract

A processor system includes a plurality of processors, along with a target device, e.g., a memory, having two or more ports, and an arbiter that arbitrates access requests from requesting processors. A multiplexer facilitates the flow of control, address and data information over a shared bus. The number of processors requesting access may be greater than the number of target ports. Each processor can issue a request for access to communicate with a target port at any time by a transaction, such as a data read or write. The arbiter may simultaneously grant access to as many requesting processors up to the number of target ports. The arbiter dynamically and arbitrarily allocates each target port to a requesting processor at the time of the request for access, which may occur within each system clock cycle, and each access may last for one or more clock cycles. The data transfer for each processor granted access may be transmitted through the target port and through the multiplexer. Depending on the arbitration method chosen, the arbiter may or may not grant equal access to all requesters, or the arbiter may or may not give equal priority to one or more requestors. By allocating the ports of a multi-port target to service the simultaneous requests of multiple processors at the time of the requests, the utilization of the target ports by the processors may be increased, and the time the requesting processors spend waiting to access the target ports may be reduced, an overall benefit being a greater utilization of access time to highly demanded device resources within the system.

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First Claim