Digital signal processing circuit having a pattern circuit for determining termination conditions
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United States of America Patent
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Dec 28, 2010
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app pub date -
May 12, 2006
filing date -
Dec 29, 2003
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Abstract
A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comparing the ALU output with the inverted pattern to produce a second output; bitwise masking the first and second outputs using a mask of a plurality of masks to produce third and fourth output bits; combining the third and fourth output bits to produce first and a second output comparison bits; and storing the first and second output comparison bits in a memory.
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