Address window support for direct memory access translation
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United States of America Patent
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Issued Date -
Dec 21, 2006
app pub date -
Jun 21, 2005
filing date -
Jun 21, 2005
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A apparatus is disclosed. The apparatus includes a remapping circuit to facilitate access of one or more I/O devices to a memory device for direct memory access (DMA) transactions. The remapping circuit includes a translation mechanism to perform memory address translations for I/O DMA transactions via address window-based translations.
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