NAND-type memory devices including recessed source/drain regions and related methods
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United States of America Patent
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Issued Date -
Jan 4, 2007
app pub date -
May 10, 2006
filing date -
Jun 29, 2005
priority date (Note) -
Abandoned
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Abstract
A NAND-type memory device may include first and second selection transistors on a semiconductor substrate and a plurality of memory cell transistors coupled in series between the first and second selection transistors. A first source/drain region may be shared between the first selection transistor and a first of the memory cell transistors, and a second source/drain region may be shared between the second selection transistor and a last of the memory cell transistors. Moreover, a portion of at least one of the first and/or second source/drain regions may be recessed relative to a surface of the semiconductor substrate. Related methods are also discussed.
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