Integrated circuit embodying a non-volatile memory cell
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United States of America Patent
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Issued Date -
Jan 11, 2007
app pub date -
Jul 6, 2005
filing date -
Jul 6, 2005
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
An integrated circuit is provided including at least one memory cell. Such memory cell, in turn, includes a transistor and a capacitor. The transistor includes a source, a drain, and a gate. Further, the capacitor includes a well and a gate. The gate of the transistor remains in communication with the gate of the capacitor. In various other embodiments, the memory cell includes a transistor and a capacitor including wells of differing types (e.g. P-type, N-type). In such embodiments, the well of the transistor abuts the well of the capacitor. In still further embodiments, for a more compact design, a diffusion region of the transistor is situated less than 2.5 .mu.m from a diffusion region of the capacitor.
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