Optimized multi-apparation assembly
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United States of America Patent
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N/A
Issued Date -
Jan 25, 2007
app pub date -
Jun 16, 2004
filing date -
Jun 20, 2003
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The invention relates to a microelectronic chip assembly ASS comprising at least three microelectronic chip ICH, TCH, BCH stacked together and on which integrated devices are formed. At least one of the chip, called intermediate chip ICH, includes via holes VH running through said chip ICH and filled with conductive material is realized from a high-ohmic substrate on which are formed devices for the functioning of at least two other microelectronic chips, called top chip TCH and bottom chip BCH. Said top and bottom chips TCH and BCH are connected by flip chip bonding respectively on top face TF and bottom face BF of said intermediate chip ICH and said via holes VH are electrically connected to pads of said top and bottom chips TCH and BCH.
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