Data link/physical layer packet buffering and flushing

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United States of America Patent

SERIAL NO

11512031

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.

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Patent Owner(s)

Patent OwnerAddress
DATASPHERE LLC12540 BROADWELL RD SUITE 2201 MILTON GA 30004

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Denton, I Claude Beaverton, OR 21 303
Primrose, Donald R Portland, OR 7 47

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