Method and structure for fabricating devices using one or more films provided by a layer transfer process and etch back

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20070032044A1
SERIAL NO

11199987

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method for fabricating one or more devices using semiconductor substrate with a cleave region. The method includes providing a substrate. In a preferred embodiment, the substrate has a thickness of semiconductor material and a surface region. In a specific embodiment, the substrate also has a cleave plane (including a plurality of particles, deposited material, or any combination of these, and the like) provided within the substrate, which defines the thickness of semiconductor material. The method includes joining the surface region of the substrate to a first handle substrate. In a preferred embodiment, the method includes initiating a controlled cleaving action at a portion of the cleave plane to detach the thickness of semiconductor material from the substrate, while the thickness of semiconductor material remains joined to the first handle substrate. The method includes processing the first handle substrate with the thickness of semiconductor material using one or more processes to form at least one integrated circuit device onto a portion of the thickness of semiconductor material. In a preferred embodiment, the processing includes high temperature semiconductor processing techniques to form conventional integrated circuits thereon. The method forms a planarized surface region overlying the thickness of semiconductor material. The method also joins the planarized surface region to a face of a second handle substrate. The method selectively removing the first handle substrate from the thickness of semiconductor material, while the face of the second handle substrate remains joined to the planarized surface region.

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Patent Owner(s)

Patent OwnerAddress
SILICON GENESIS CORPORATION61 DAGGETT DRIVE SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Henley, Francois J Aptos, CA 178 9676

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