Non-contact etch annealing of strained layers

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United States of America Patent

SERIAL NO

11594536

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Abstract

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The present invention provides a method of forming a strained semiconductor layer. The method comprises growing a strained first semiconductor layer, having a graded dopant profile, on a wafer, having a first lattice constant. The dopant imparts a second lattice constant to the first semiconductor layer. The method further comprises growing a strained boxed second semiconductor layer having the second lattice constant on the first semiconductor layer and growing a sacrificial third semiconductor layer having the first lattice constant on the second semiconductor layer. The method further comprises etch annealing the third and second semiconductor layer, wherein the third semiconductor layer is removed and the second semiconductor layer is relaxed. The method may further comprises growing a fourth semiconductor layer having the second lattice constant on the second semiconductor layer, wherein the fourth semiconductor layer is relaxed, and growing a strained fifth semiconductor layer having the first semiconductor lattice constant on the fourth semiconductor layer. The method controls the surface roughness of the semiconductor layers. The method also has the unexpected benefit of reducing dislocations in the semiconductor layers.

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Patent Owner(s)

Patent OwnerAddress
SILICON GENESIS CORPORATIONSAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Henley, Francois Aptos, CA 6 476
Malik, Igor Palo Alto, CA 3 425
Ong, Philip Milpitas, CA 3 443

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