Embedded SiGe stressor with tensile strain for NMOS current enhancement
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United States of America Patent
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Nov 3, 2009
Grant Date -
Mar 15, 2007
app pub date -
Sep 15, 2005
filing date -
Sep 15, 2005
priority date (Note) -
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Abstract
MOS devices having localized stressors are provided. Embodiments of the invention comprise a gate electrode formed over a substrate and source/drain regions formed on either side of the gate electrode. The source/drain regions include an embedded stressor and a capping layer on the embedded stressor. Preferably, the embedded stressor has a lattice spacing greater than the substrate lattice spacing. In a preferred embodiment, the substrate is silicon and the embedded stressor is silicon germanium. A method of manufacturing is also provided, wherein strained PMOS and NMOS transistors may be formed simultaneously.
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