CONTROLLED DEPTH ETCHED VIAS
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United States of America Patent
Stats
-
N/A
Issued Date -
Mar 22, 2007
app pub date -
Jan 9, 2006
filing date -
Aug 22, 2005
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A printed circuit board (20) includes a sub-assembly having dielectric (22) and conductive layers (24). A hole (26) extends into the sub-assembly. Metal plating (32) is applied on a barrel (27) of the hole (26). A conductive layer (32) and an etch resist (34) are applied to a first photoresist (30) on the hole barrel (27). The first photoresist (30) is removed and a second photoresist (36) is applied leaving areas to be controlled depth etched exposed. The exposed areas (38) are chemically etched. The second layer of photoresist (36) is removed and a second chemical etch operation is performed to define previously plated features (40) on the sub-assembly (20). The etch resist (34) is then removed.
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Cited Art Landscape
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