BGA package with stacked semiconductor chips and method of manufacturing the same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 5, 2009
Grant Date -
Mar 22, 2007
app pub date -
Nov 22, 2006
filing date -
Jul 18, 2003
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A package with two or more stacked semiconductor chips and a method of manufacturing the same. In the method, an upper semiconductor chip package and a lower semiconductor chip package are prepared. Solder balls are formed on a substrate of the lower package to connect the upper and lower packages. A semiconductor chip and the solder balls are molded and then ground until the solder balls are exposed. Solder balls are formed on the bottom of a substrate of the upper package. The upper package is stacked on the lower package such that the solder balls of the lower package are in contact with the solder balls of the upper package. A reflow process is performed on the lower package and the upper package, which are stacked, to physically connect the upper and lower packages.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully