Hardware acceleration system for logic simulation using shift register as local cache with path for bypassing shift register
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United States of America Patent
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app pub date -
Nov 30, 2005
filing date -
Sep 28, 2005
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Abandoned
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Abstract
A simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. Each of the processor units includes a processor element configurable to simulate at least a logic operation, and a shift register for storing intermediate values generating during the logic simulation. Each of the processor units further includes one or more multiplexers for selecting one of the entries of the shift register as outputs to be coupled to the interconnect system. Each of the processor units can also include one or more bypass multiplexers coupled between the output of the processor element and the interconnect system, for providing a path for bypassing the shift register to provide the output of the processor element directly to the interconnect system.
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