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Abstract

Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area and power constraints in an electronic design system. The IP Generator receives a user-supplied file having data describing a configuration of an intellectual property (IP) design, the data includes one or more configuration parameters. The IP Generator further enables a transformation of the user-supplied file into a register transfer level design description. Next, the IP Generator receives user-supplied technology parameters and data-flow information. The technology parameters describe a configuration of the IP design. Next, the IP Generator executes a timing module based on the configuration of the IP design as well as executes a timing model for each hierarchical level in the IP design. The timing model predicts timing paths of a final logic circuit. Further, a result of the timing model is provided to the user prior to enabling a transformation of a register transfer level design into the simulation of a gate-level circuit design. Lastly, after the timing model has been executed, is the enablement of the transformation of the register transfer level design into the simulation of the gate-level circuit design.

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