Block serial pipelined layered decoding architecture for structured low-density parity-check (LDPC) codes
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United States of America Patent
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Issued Date -
Apr 19, 2007
app pub date -
Oct 18, 2005
filing date -
Oct 18, 2005
priority date (Note) -
Abandoned
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Abstract
An error correction decoder for block serial pipelined layered decoding of block codes includes primary and mirror memories that are each capable of storing log-likelihood ratios (LLRs) for one or more iterations of an iterative decoding technique. The decoder also includes a plurality of elements capable of processing, for one or more iterations, one or more layers of a parity-check matrix. The elements include an iterative decoder element capable of calculating, for one or more iterations or layers, a LLR adjustment based upon the LLR for a previous iteration/layer, the LLR for the previous iteration/layer being read from the primary memory. The decoder further includes a summation element capable of reading the LLR for the previous iteration/layer from the mirror memory, and calculating the LLR for the iteration/layer based upon the LLR adjustment for the iteration/layer and the previous iteration/layer LLR for the previous iteration/layer.
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