Error correction decoder, method and computer program product for block serial pipelined layered decoding of structured low-density parity-check (LDPC) codes, including reconfigurable permuting/de-permuting of data values
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United States of America Patent
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app pub date -
Nov 14, 2005
filing date -
Oct 18, 2005
priority date (Note) -
Abandoned
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Abstract
An error correction decoder for block serial pipelined layered decoding of block codes includes a plurality of elements capable of processing, for at least one of a plurality of iterations of an iterative decoding technique, at least one layer of a parity check matrix. The elements can include a permuter and/or de-permuter capable of permuting and/or depermuting, for at least one iteration or at least one layer of the parity-check matrix, at least one data array. The permuter/de-permuter can include a permuting Benes network and a sorting Benes network. In this regard, the permuting Benes network can include a plurality of switches for permuting the LLR for the previous iteration or layer, or de-permuting the portion of the LLR for the iteration or layer. Driving the permuting Benes network, then, the sorting Benes network can be capable of generating control logic for the switches of the permuting Benes network.
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