Error correction decoder, method and computer program product for block serial pipelined layered decoding of structured low-density parity-check (LDPC) codes, including calculating check-to-variable messages

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United States of America Patent

SERIAL NO

11273552

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Abstract

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An error correction decoder for block serial pipelined layered decoding of block codes includes a plurality of elements capable of processing, for at least one of a plurality of iterations of an iterative decoding technique, at least one layer of a parity check matrix. The elements include an iterative decoder element capable of calculating, for one or more iterations or one or more layers of the parity-check matrix, a check-to-variable message. Calculating the check-to-variable message can include calculating a magnitude of the check-to-variable message based upon a first minimum magnitude, a second minimum magnitude and a third minimum magnitude of a plurality of variable-to-check messages for a previous iteration or layer.

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Patent Owner(s)

Patent OwnerAddress
NOKIA CORPORATION02610 ESPOO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bhatt, Tejas Irving, TX 17 606
Sundaramurthy, Vishwas Irving, TX 6 264
Tang, Jun Minneapolis, MN 147 1315

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