Memory controller
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United States of America Patent
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Jan 18, 2011
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N/A
app pub date -
Nov 15, 2004
filing date -
Dec 9, 2003
priority date (Note) -
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Abstract
The present invention relates to a memory controller for an IC with an external DRAM, where the external DRAM has at least one memory bank and communicates with the IC via at least one channel. In line with the invention, the memory controller has a command scheduler which prioritizes the transmission of memory bank commands on the basis of a static priority allocation for commands and a dynamic priority allocation for channels.
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