Method of manufacturing symmetric arrays
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United States of America Patent
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Issued Date -
May 3, 2007
app pub date -
Sep 7, 2006
filing date -
Sep 8, 2005
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Abandoned
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Abstract
A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area, an oxide-nitride-oxide (ONO) layer within the word line areas and at least partially within the contact areas and protective elements, generated when spacers are formed in the periphery area, to protect silicon under the ONO layer in the contact areas. A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area and bit line oxides whose height is at least a quarter of the distance between neighboring bit line oxides.
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