Method and/or apparatus to detect and handle defects in a memory
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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N/A
Issued Date -
May 24, 2007
app pub date -
Mar 16, 2006
filing date -
Nov 10, 2005
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
An apparatus comprising a memory circuit, a test circuit, an interface circuit and a defect handler circuit. The memory circuit may be configured to store and retrieve data in response to (i) a data signal, (ii) a test data signal, (iii) an address signal, (iv) a first control signal and (v) a write signal. The test circuit may be configured to generate the test data signal in response to the address signal. The interface circuit may be configured to generate the control signal in response to (i) the address signal, (ii) a read signal, and (iii) the write signal. The defect handler circuit may be configured to redirect data read from the memory circuit in response to (i) the address signal, (ii) the data signal and (iii) the write signal.
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