RECONFIGURABLE PROCESSING ARRAY HAVING HIERARCHICAL COMMUNICATION NETWORK
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United States of America Patent
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app pub date -
Nov 7, 2006
filing date -
Jun 18, 2003
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Abandoned
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Abstract
A processor includes multiple compute units and memory units arranged in groups of abutted tiles. Multiple tiles are arranged together along with input/output interfaces to form a processor system that can be configured to perform many different operations. A hierarchical communication network efficiently connects components within the tiles and between multiple tiles.
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