Hardware acceleration system for simulation of logic and memory
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United States of America Patent
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Issued Date -
Jun 7, 2007
app pub date -
Dec 1, 2005
filing date -
Dec 1, 2005
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A hardware-accelerated simulator includes a storage memory and a program memory that are separately accessible by the simulation processor. The program memory stores instructions to be executed in order to simulate the chip. The storage memory is used to simulate the user memory. Since the program memory and storage memory are separately accessible by the simulation processor, the simulation of reads and writes to user memory does not block the transfer of instructions between the program memory and the simulation processor, thus increasing the speed of simulation. In one aspect, user memory addresses are mapped to storage memory addresses by adding a fixed, predetermined offset to the user memory address. Thus, no address translation is required at run-time.
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