Active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices
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United States of America Patent
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Oct 14, 2008
Grant Date -
Jun 28, 2007
app pub date -
Dec 27, 2005
filing date -
Dec 27, 2005
priority date (Note) -
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Abstract
A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.
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