Dynamic host code generation from architecture description for fast simulation

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United States of America Patent

PATENT NO 9830174
SERIAL NO

11584402

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Abstract

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Systems and methods of dynamic host code generation from architecture description for fast simulation. In accordance with a method embodiment of the present invention, a method of simulating execution of a first plurality of processor instructions written in a first instruction set comprises generating a second plurality of processor instructions in a second instruction set for emulating the first plurality of processor instructions. The generating is based upon the high level description of the instruction set and/or simulated state information during the simulating.

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Patent Owner(s)

  • SYNOPSYS, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Luthje, Olaf Aachen, DE 1 1
Nohl, Achim Aachen, DE 11 99
Van, Damme Jacques Heverlee, BE 1 0

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