Characterization and verification for integrated circuit designs
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 4, 2010
Grant Date -
Jul 5, 2007
app pub date -
Feb 6, 2007
filing date -
Jun 7, 2002
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully