Semiconductor package, substrate with conductive post, stacked type semiconductor device, manufacturing method of semiconductor package and manufacturing method of stacked type semiconductor device
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United States of America Patent
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Issued Date -
Jul 19, 2007
app pub date -
Jan 18, 2007
filing date -
Jan 19, 2006
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A semiconductor package comprising: a substrate containing a wiring pattern connected to a plurality of external electrodes; one or more semiconductor chips connected to the wiring pattern and mounted on the substrate; a conductive post connected to a predetermined the external electrode and functioning as a relay electrode in a vertical direction; and a resin sealing layer for integrally sealing the semiconductor chips and the conductive post in a state in which an upper end face of the conductive post is exposed.
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