Memory circuit arrangement and method for reading and/or verifying the status of memory cells of a memory cell array
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United States of America Patent
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Issued Date -
Aug 2, 2007
app pub date -
Jan 30, 2006
filing date -
Jan 30, 2006
priority date (Note) -
Abandoned
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Abstract
A memory circuit arrangement includes a memory cell array having a plurality of memory cells. A memory read/verify control circuit controls a read operation and/or a verify operation on one or a plurality of memory cells of the memory cell array. The memory read/verify control circuit is adapted to read and/or verify the status of each memory cell of the memory cell array according to read and/or verify instruction information on memory cell level.
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