Wafer level packaging to lidded chips
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United States of America Patent
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N/A
Issued Date -
Aug 16, 2007
app pub date -
Jan 19, 2007
filing date -
Jan 23, 2006
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
Methods are provided for making a plurality of lidded microelectronic elements. In an exemplary embodiment, a lid wafer is assembled with a device wafer. Desirably, the lid wafer is severed into a plurality of lid elements to remove portions of the lid wafer overlying contacts at a front face of the device wafer adjacent to dicing lanes of the device wafer. Thereafter, desirably, the device wafer is severed along the dicing lanes to provide a plurality of lidded microelectronic elements.
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