Shallow trench isolation (STI) devices and processes
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United States of America Patent
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Issued Date -
Aug 30, 2007
app pub date -
Feb 24, 2006
filing date -
Feb 24, 2006
priority date (Note) -
Abandoned
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Abstract
Improved shallow trench isolation (STI) techniques are provided for semiconductor devices. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a substrate, a first trench in the substrate, and a second trench in the substrate. A first transistor region in the substrate is adjacent to and between the first and second trenches. A silicon dioxide liner substantially lines the first and second trenches. A silicon nitride liner is on the silicon dioxide liner in the first trench but not on the silicon dioxide liner in the second trench. A dielectric material fills the first and second trenches.
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