Method for accelerating the RC extraction in integrated circuit designs
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United States of America Patent
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Issued Date -
Aug 30, 2007
app pub date -
Aug 7, 2006
filing date -
Feb 24, 2006
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The present invention provides a system and method for accelerating the resistance and capacitance (RC) extraction process by performing parallel and distributed processing. The method includes the dividing of a given integrated circuit (IC) design into a limited number of non-overlapping tile blocks, distributing tile blocks to standard RC extraction tools, and processing all tiles in parallel by these tools. A tile block includes all information for performing accurate RC extraction. Thereafter, resulting parasitic RC information is assembled to form a complete parasitic RC model for the entire IC.
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