Memory cells in double-gate CMOS technology provided with transistors with two independent gates

United States of America Patent

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Mar 31, 2009
Grant Date
Sep 13, 2007
app pub date
Mar 8, 2007
filing date
Mar 10, 2006

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Expired

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Abstract

This invention relates to an improved microelectronic RAM memory device, provided with 4T or 6T cells made using the double gate technology and each associated with two word lines.

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Patent Owner	Address
COMMISSARIAT A L'ENERGIE ATOMIQUE	31/33 RUE DE LA FEDERATION 75015 PARIS

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G11C:STATIC STORES

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Inventor Name	Address	# of filed Patents	Total Citations
Belleville, Marc	Saint-Egreve, FR	21	350
Thomas, Olivier	Revel, FR	39	1215

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Memory cells in double-gate CMOS technology provided with transistors with two independent gates

Number of patents in Portfolio can not be more than 2000

United States of America Patent

11683722

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PATENT NO	7511989
APP PUB NO	20070211519A1
SERIAL NO	11683722
DOCKET NO

US Family Size	Non-US Coverage
Patent Longevity Expired	Forward Citations

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
March 31, 2009	US,7511989,B2 US7511989B2	GRANTED PATENT AS SECOND PUBLICATION
September 13, 2007	US,20070211519,A1 US20070211519A1	FIRST PUBLISHED PATENT APPLICATION

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11683722

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