MEMORY DEVICE AND RELATIVE CONTROL METHOD
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United States of America Patent
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Issued Date -
Sep 20, 2007
app pub date -
Feb 21, 2007
filing date -
Feb 22, 2006
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A single job memory device includes an array of memory cells, row and column decoders and first and second charge pump voltage regulators controlled by respective first and second control circuits that supply the row and column decoders at least during write operations of data in the array of memory cells. A third charge pump voltage generator, controlled by a third control circuit, supplies the row and column decoders during read operations of data from the array of memory cells. The memory device includes a switching circuit that, during the read operations, disconnects two of the control circuits from the respective charge pump voltage generators, transmits control signals generated by the other control circuit to the first and second charge pump voltage generators, and shorts among them the output nodes of the voltage generators on which the supply voltages of the row and column decoders are generated.
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