Method for column redundancy using data latches in solid-state memories
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United States of America Patent
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Jul 1, 2008
Grant Date -
Sep 27, 2007
app pub date -
Mar 24, 2006
filing date -
Mar 24, 2006
priority date (Note) -
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Abstract
A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.
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