Multi-portioned instruction memory
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United States of America Patent
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N/A
Issued Date -
Oct 4, 2007
app pub date -
Mar 31, 2006
filing date -
Mar 31, 2006
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
An instruction memory for storing a plurality of instruction bits. A first portion of the instruction memory is for storing a first subset of bits of the plurality of instruction bits. A second portion of the instruction memory is for storing a second subset of bits of the plurality of instruction bits, wherein the second subset of bits is operable to be accessed by an instruction extractor during an instruction extraction earlier than the first subset of bits.
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