Method to control source/drain stressor profiles for stress engineering
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United States of America Patent
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Sep 13, 2011
Grant Date -
Oct 11, 2007
app pub date -
Apr 5, 2006
filing date -
Apr 5, 2006
priority date (Note) -
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Abstract
A strained channel transistor structure and methods of forming a semiconductor device are presented. The transistor structure includes a strained channel region having a first semiconductor material with a first natural lattice constant. A gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer and a source region and drain region oppositely adjacent to the strained channel region are provided. One or both of the source region and drain region include a stressor region having a second semiconductor material with a second natural lattice constant different from the first natural lattice constant. The stressor region has graded concentration of a dopant impurity and/or of a stress inducing molecule.
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