INTEGRATED CIRCUIT PACKAGE SYSTEM WITH POST-PASSIVATION INTERCONNECTION AND INTEGRATION

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United States of America Patent

APP PUB NO 20070235878A1
SERIAL NO

11278002

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Abstract

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An integrated circuit package system is provided providing an integrated circuit die having a final metal layer of the semiconductor process used to manufacture the integrated circuit die and a passivation layer provided thereon, depositing a first metal layer on the passivation layer and the final metal layer, forming an analog circuit in the first metal layer, coating a first insulation layer on the first metal layer and the passivation layer, exposing a first pad and a second pad of the first metal layer through the first insulation layer, and connecting a first interconnect on the first pad and a second interconnect on the second pad.

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Patent Owner(s)

Patent OwnerAddress
STATS CHIPPAC PTE LTD5 YISHUN STREET 23 SINGAPORE 768442

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lin, Yaojian Singapore, SG 330 9795
Marimuthu, Pandi Chelvam Singapore, SG 45 1837

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