Interrupt routing within multiple-processor system
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United States of America Patent
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Issued Date -
Oct 11, 2007
app pub date -
Dec 9, 2005
filing date -
Dec 9, 2005
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Interrupts are routed within a multiple-processor system, such as a single computing device having multiple processors. Such a computerized system includes a number of processors and a mechanism. Each processor is capable of processing an interrupt. The mechanism, such as a Southbridge controller, receives the interrupt and routes it to a selected processor. The selected processor processes the interrupt via entry into a mode related to the interrupt. The interrupt may be a system management interrupt (SMI), and the mode a system management mode (SMM). The other processors operate normally and are not affected by processing of the interrupt, and do not have to enter the mode. These other processors can continue executing code as before, and may receive and process other types of interrupts. The system may include another mechanism, such as a complex programmable logic device (CPLD), specifying the selected processor.
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