US Patent Application No: 2007/0252,617

Number of patents in Portfolio can not be more than 2000

VERSATILE LOGIC ELEMENT AND LOGIC ARRAY BLOCK

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Abstract

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An embodiment of this invention pertains to a versatile and flexible logic element and logic array block ('LAB'). Each logic element includes a programmable combinational logic function block such as a lookup table ('LUT') and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an 'add-or-subtract control signal' that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
ALTERA CORPORATIONSAN JOSE, CA3834

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Betz, Vaughn Toronto, CA 90 768
Kim, Henry San Jose, US 32 240
Lane, Christopher F San Jose, US 70 1595
Lee, Andy L San Jose, US 132 1877
Leventis, Paul Toronto, CA 38 383
Lewis, David M Toronto, CA 31 866
Marquardt, ALexander Toronto, CA 5 71
Pedersen, Bruce San Jose, US 62 1002
Santurkar, Vikram San Jose, US 23 183
Wysocki, Chris Toronto, CA 15 101

Cited Art Landscape

Patent Info (Count) # Cites Year
 
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QUICKTURN DESIGN SYSTEMS, INC. (1)
* 6,184,707 Look-up table based logic element with complete permutability of the inputs to the secondary signals 164 1998
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
NORTH DAKOTA STATE UNIVERSITY (1)
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PANASONIC CORPORATION (1)
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ALTERA CORPORATION (3)
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NVIDIA CORPORATION (1)
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XILINX, INC. (10)
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HITACHI, LTD. (2)
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* Cited By Examiner