US Patent Application No: 2007/0252,617

Number of patents in Portfolio can not be more than 2000






Loading Importance Indicators... loading....


See full text

An embodiment of this invention pertains to a versatile and flexible logic element and logic array block ('LAB'). Each logic element includes a programmable combinational logic function block such as a lookup table ('LUT') and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an 'add-or-subtract control signal' that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

Loading the Abstract Image... loading....

First Claim

See full text

all claims..


Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]


Inventor Name Address # of filed Patents Total Citations
Betz, Vaughn Toronto, CA 112 639
Kim, Henry San Jose, CA 35 198
Lane, Christopher F San Jose, CA 84 1467
Lee, Andy L San Jose, CA 166 1659
Leventis, Paul Toronto, CA 56 323
Lewis, David M Toronto, CA 37 755
Marquardt, Alexander Toronto, CA 7 60
Pedersen, Bruce Sunnyvale, CA 81 913
Santurkar, Vikram Fremont, CA 32 154
Wysocki, Chris Toronto, CA 16 83

Cited Art Landscape

  • No Cited Art to Display

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
8,706,793 Multiplier circuits with optional shift function 1 2009
8,527,572 Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same 0 2009
7,982,496 Bus-based logic blocks with optional constant input 1 2009
7,948,265 Circuits for replicating self-timed logic 3 2009
7,746,101 Cascading input structure for logic blocks in integrated circuits 4 2009
7,746,108 Compute-centric architecture for integrated circuits 5 2009
7,746,109 Circuits for sharing self-timed logic 4 2009
* 7,746,110 Circuits for fanning out data in a programmable self-timed integrated circuit 6 2009
8,402,164 Asynchronous communication network and methods of enabling the asynchronous communication of data in an integrated circuit 1 2010
8,514,994 Double data rate operation in an integrated circuit 0 2008
7,948,792 Memory and techniques for using same 2 2009
* 8,219,844 Methods and systems for emulating a synchronous clear port 0 2009
* 8,698,140 Semiconductor device, and test method for same 0 2010
* 7,956,639 Intelligent cellular electronic structures 1 2009
* 7,622,947 Redundant circuit presents connections on specified I/O ports 1 2006
* Cited By Examiner