Versatile logic element and logic array block

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO

7432734

APP PUB NO

20070252617A1

SERIAL NO

11743625

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An embodiment of this invention pertains to a versatile and flexible logic element and logic array block ('LAB'). Each logic element includes a programmable combinational logic function block such as a lookup table ('LUT') and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an 'add-or-subtract control signal' that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
ALTERA CORPORATIONSAN JOSE, CA4091

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Betz, Vaughn Toronto, CA 93 909
Kim, Henry San Jose, CA 33 274
Lane, Christopher F San Jose, CA 72 1662
Lee, Andy L San Jose, CA 138 2025
Leventis, Paul Toronto, CA 38 429
Lewis, David M Toronto, CA 31 912
Marquardt, Alexander Toronto, CA 5 74
Pedersen, Bruce San Jose, CA 64 1069
Santurkar, Vikram San Jose, CA 24 208
Wysocki, Chris Toronto, CA 16 108

Cited Art Landscape

Patent Info (Count) # Cites Year
 
LATTICE SEMICONDUCTOR CORPORATION (1)
* 6380759 Variable grain architecture for FPGA integrated circuits 46 2000
 
MONTEREY RESEARCH, LLC (1)
6211696 Hybrid product term and look-up table-based programmable logic device with improved speed and area efficiency 12 1998
 
Cadence Design Systems, Inc. (1)
5821773 Look-up table based logic element with complete permutability of the inputs to the secondary signals 47 1995
 
ALTERA CORPORATION (26)
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6275065 Programmable logic integrated circuit architecture incorporating a lonely register 64 2000
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6271680 Logic element for a programmable logic integrated circuit 18 2000
6344755 Programmable logic device with redundant circuitry 47 2000
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XILINX, INC. (18)
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* 5682107 FPGA architecture with repeatable tiles including routing matrices and logic matrices 230 1996
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6167558 Method for tolerating defective logic blocks in programmable logic devices 55 1998
6020756 Multiplexer enhanced configurable logic block 14 1998
6118300 Method for implementing large multiplexers with FPGA lookup tables 66 1998
6051992 Configurable logic element with ability to evaluate five and six input functions 34 1999
6201410 Wide logic gate implemented in an FPGA configurable logic element 15 1999
6124731 Configurable logic element with ability to evaluate wide logic functions 30 2000
6191610 Method for implementing large multiplexers with FPGA lookup tables 29 2000
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QUICKTURN DESIGN SYSTEMS, INC. (1)
6184707 Look-up table based logic element with complete permutability of the inputs to the secondary signals 166 1998
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
CALLAHAN CELLULAR L.L.C. (2)
* 7573294 Programmable logic based latches and shift registers 1 2008
* 2009/0167,350 PROGRAMMABLE LOGIC BASED LATCHES AND SHIFT REGISTERS 0 2008
 
ALTERA CORPORATION (1)
* 7671626 Versatile logic element and logic array block 0 2008
 
NVIDIA CORPORATION (1)
* 7622947 Redundant circuit presents connections on specified I/O ports 1 2006
 
XILINX, INC. (2)
* 7991909 Method and apparatus for communication between a processor and processing elements in an integrated circuit 5 2007
7917876 Method and apparatus for designing an embedded system for a programmable logic device 1 2007
* Cited By Examiner

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11.5 Year Payment $7400.00 $3700.00 $1850.00 Apr 7, 2020
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