US Patent Application No: 2007/0252,617

Number of patents in Portfolio can not be more than 2000

VERSATILE LOGIC ELEMENT AND LOGIC ARRAY BLOCK

ALSO PUBLISHED AS: 7432734

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Abstract

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An embodiment of this invention pertains to a versatile and flexible logic element and logic array block ("LAB"). Each logic element includes a programmable combinational logic function block such as a lookup table ("LUT") and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an "add-or-subtract control signal" that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
ALTERA CORPORATIONSAN JOSE, CA3340

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Betz, Vaughn Toronto, CA 107 602
Kim, Henry San Jose, CA 34 183
Lane, Christopher F San Jose, CA 82 1409
Lee, Andy L San Jose, CA 161 1567
Leventis, Paul Toronto, CA 55 309
Lewis, David M Toronto, CA 37 710
Marquardt, Alexander Toronto, CA 7 59
Pedersen, Bruce Sunnyvale, CA 80 864
Santurkar, Vikram Fremont, CA 32 148
Wysocki, Chris Toronto, CA 16 79

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
XILINX, INC. (9)
8,706,793 Multiplier circuits with optional shift function 0 2009
8,527,572 Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same 0 2009
7,982,496 Bus-based logic blocks with optional constant input 0 2009
7,948,265 Circuits for replicating self-timed logic 3 2009
7,746,101 Cascading input structure for logic blocks in integrated circuits 3 2009
7,746,108 Compute-centric architecture for integrated circuits 3 2009
7,746,109 Circuits for sharing self-timed logic 3 2009
7,746,110 Circuits for fanning out data in a programmable self-timed integrated circuit 5 2009
8,402,164 Asynchronous communication network and methods of enabling the asynchronous communication of data in an integrated circuit 1 2010
 
ALTERA CORPORATION (3)
8,514,994 Double data rate operation in an integrated circuit 0 2008
7,948,792 Memory and techniques for using same 2 2009
8,219,844 Methods and systems for emulating a synchronous clear port 0 2009
 
HITACHI, LTD. (1)
8,698,140 Semiconductor device, and test method for same 0 2010
 
NORTH DAKOTA STATE UNIVERSITY (1)
7,956,639 Intelligent cellular electronic structures 1 2009
 
NVIDIA CORPORATION (1)
7,622,947 Redundant circuit presents connections on specified I/O ports 1 2006

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