Ferroelectric memory with sub bit-lines connected to each other and to fixed potentials
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 7, 2009
Grant Date -
Nov 1, 2007
app pub date -
Apr 25, 2007
filing date -
Apr 26, 2006
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully