Memory Arrangement And Method For Error Correction

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United States of America Patent

APP PUB NO 20070255999A1
SERIAL NO

11696745

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Abstract

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A method of error correction for a memory arrangement includes dividing information to be written to the memory arrangement into n data blocks of m bits each, writing the n data blocks to at least one memory module of the memory arrangement, determining a redundant data block based on the n data blocks, writing the redundant data block to a further memory module of the memory arrangement, reading the n data blocks, and checking for errors in the read n data blocks including detecting a faulty data block in the read n data blocks. If an error is detected, the method includes reading the redundant information in advance from the at least one further memory module and determining all bits of the faulty data block from the n data blocks and the redundant data block.

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Patent Owner(s)

Patent OwnerAddress
QIMONDA AG81739 MÜNCHEN

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Risse, Gerhard Munchen, DE 11 83

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