Relative Floorplanning For Improved Integrated Circuit Design
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United States of America Patent
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Issued Date -
Nov 15, 2007
app pub date -
May 14, 2007
filing date -
May 15, 2006
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A method for designing integrated circuits includes receiving a floorplan design associated with an integrated circuit. A relative floorplanning constraint is extracted from the floorplan design. The floorplan of the integrated circuit is updated in response to the relative floorplanning constraint. Another method for designing integrated circuits includes receiving a floorplan design associated with an integrated circuit. A set of relative floorplanning constraint is received from the floorplan design. A relative floorplanning constraint is pushed down from the set of relative floorplanning constraints into a partition associated with the floorplan of the integrated circuit. The floorplan is updated in response to the set of relative floorplanning constraints.
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