NAND type flash memory
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United States of America Patent
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Apr 14, 2009
Grant Date -
Dec 6, 2007
app pub date -
May 16, 2007
filing date -
May 18, 2006
priority date (Note) -
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Abstract
A NAND type flash memory included with a memory cell array composed of a plurality of electronically rewritable memory cells arranged in a matrix shape, and a data inversion control section which judges whether a polarity of a “1” data or a “0” data is to be inverted based on the number of the “1” data and the “0” data of the data when data is sent to the plurality of memory cells within a simultaneous write data unit and inverts the data and in the case where it is sent to the memory cell array adds an inversion flag bit to the data which shows the inversion of the polarity.
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