METHOD FOR FABRICATING DOPED POLYSILICON LINES

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United States of America Patent

SERIAL NO

11835745

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Abstract

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A method of fabricating polysilicon lines and polysilicon gates, the method of including: forming a dielectric layer on a top surface of a substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species essentially contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Adkisson, James W Jericho, VT 161 2202
Ellis-Monaghan, John J Grand Isle, VT 186 1539
MacDougall, Glenn C Essex Junction, VT 5 37
Martin, Dale W Hyde Park, VT 23 456
Peterson, Kirk D Jericho, VT 124 668
Porth, Bruce W Jericho, VT 20 19

Cited Art Landscape

Patent Info (Count) # Cites Year
 
TEXAS INSTRUMENTS-ACER INCORPORATED (1)
* 5930617 Method of forming deep sub-micron CMOS transistors with self-aligned silicided contact and extended S/D junction 43 1998
 
ADVANCED MICRO DEVICES, INC. (2)
* 6051459 Method of making N-channel and P-channel IGFETs using selective doping and activation for the N-channel gate 11 1997
* 6373113 Nitrogenated gate structure for improved transistor performance and method for making same 14 1998
 
INTEGRATED DEVICE TECHNOLOGY, INC. (1)
* 5780330 Selective diffusion process for forming both n-type and p-type gates with a single masking step 35 1996
 
LUCENT TECHNOLOGIES INC. (2)
* 6121124 Process for fabricating integrated circuits with dual gate devices therein 12 1998
* 6174807 Method of controlling gate dopant penetration and diffusion in a semiconductor device 11 1999
 
UNITED MICROELECTRONICS CORP. (1)
* 6399456 Method of fabricating a resistor and a capacitor electrode in an integrated circuit 1 1998
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (1)
* 6436771 Method of forming a semiconductor device with multiple thickness gate dielectric layers 47 2001
 
GLOBALFOUNDRIES INC. (3)
* 5872049 Nitrogenated gate structure for improved transistor performance and method for making same 9 1996
* 5885877 Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric 67 1997
* 5936287 Nitrogenated gate structure for improved transistor performance and method for making same 10 1998
 
TEXAS INSTRUMENTS INCORPORATED (1)
* 6352900 Controlled oxide growth over polysilicon gates for improved transistor characteristics 4 2000
* Cited By Examiner

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
Inpower Semiconductor Co., Ltd. (3)
7799642 Trench MOSFET and method of manufacture utilizing two masks 0 2007
* 7687352 Trench MOSFET and method of manufacture utilizing four masks 2 2007
* 2009/0085,074 TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING FOUR MASKS 12 2007
 
APPLIED MATERIALS, INC. (2)
* 9390930 Surface stabilization process to reduce dopant diffusion 0 2012
* 2013/0109,162 SURFACE STABILIZATION PROCESS TO REDUCE DOPANT DIFFUSION 2 2012
* Cited By Examiner