METHOD FOR FABRICATING DOPED POLYSILICON LINES

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United States of America Patent

SERIAL NO

11835745

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Abstract

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A method of fabricating polysilicon lines and polysilicon gates, the method of including: forming a dielectric layer on a top surface of a substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species essentially contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.

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Patent Owner(s)

Patent OwnerAddress
ADKISSON JAMES WNot Provided

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Adkisson, James W Jericho, VT 161 2257
Ellis-Monaghan, John J Grand Isle, VT 190 1574
MacDougall, Glenn C Essex Junction, VT 5 37
Martin, Dale W Hyde Park, VT 23 463
Peterson, Kirk D Jericho, VT 130 688
Porth, Bruce W Jericho, VT 21 21

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